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Western Digital announces 96-layer 3D NAND; up to 128GB per chip!

Western Digital announces 96-layer 3D NAND; up to 128GB per chip!

by Vyncent ChanJune 28, 2017
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Western Digital has just announced their next-generation BiCS4 3D NAND technology with 96 layers of vertical scalability, the successor to their 3rd generation BiCS3 3D NAND which was capable of up to scaling up 64 layers. The new technology is expected to be sampled by OEM customers in the second half of 2017, with production to start in 2018.

The new technology will initially be available as 256Gb (32GB) chips, with up to 1Tb (128GB) per chip on the horizon. The new 3D NAND chips will use triple level cell (TLC) and a new quadruple level cell (QLC) architecture. This means that each cell can store up to 4 bits (16 voltage states). Understandably, durability for QLC will be even lesser than TLC, but the technology may be implemented in applications that will not see much write operations.

BiCS4 allows for a capacity increase of approximately 40% given the same chip footprint, lowering the cost per bit of storage and also increases the manufacturability of memory capacity per silicon wafer. Western Digital plans to gradually introduce higher density BiCS4 3D NAND chips, before moving on to BiCS5 in 2020.

Pokdepinion: QLC looks like something that can allow SSDs to fully take over from HDDs. Maybe we can have them as dirt cheap boot drives? Or better yet, a hybrid configuration, but maybe with up to 64GB of QLC 3D NAND?

About The Author
Vyncent Chan
Technology enthusiast, casual gamer, pharmacy graduate. Strongly opposes proprietary standards and always on the look out for incredible bang-for-buck.

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