Intel Meteor Lake To Use A New L4 “Adamantine” Cache
Intel Meteor Lake To Use A New L4 “Adamantine” Cache
The new level of cache is designed for specific functions, though.
Intel’s upcoming Meteor Lake CPUs has been confirmed to use the L4 cache, its first since the short-lived Broadwell-based Core i7-5775C (which featured 128MB eDRAM as the L4). However, this time around the new chip will be using an entirely different packaging technique according to the patent filings.
The patent, dated back to December 2020, explains how the L4 cache work on the ‘next-generation SoC architecture’ (or Meteor Lake as we know it today). The L4 cache will be placed on-package, meaning it could be a part of the ‘base tile’ (denoted as ‘ADM base’ in the diagram below) that connects multiple ’tiles’ of the chip – including iGPU tile, SoC tile, I/O tile and CPU core tile.
That being said, the L4 cache will not be used as a general-purpose cache to feed the CPU during general compute. Instead, this type of cache will be used in special functions, including boot optimizations and chip-level security enhancements. The cache data will get preserved during reset, which means a system boot/reboot can be sped up significantly as opposed to current boot cycles. Leaks has indicate that the size of L4 cache are starting from 128MB, though it’s possible to expanded into gigabyte-range and it’s currently being tested.
The diagram also shows the package denoting RWC core and CMT core – which stands for Redwood Cove (P-core) and Crestmont (E-core) respectively. Interestingly, the same Crestmont cores can be seen on the SoC tile, but we don’t know what’s the intended purpose of those cores just yet, apart from the fact that it’s likely ultra low-power versions of the same core.
Intel’s Meteor Lake CPUs are likely set for 2H 2023 launch, however the company didn’t specify which segment these product will be launched first.
Source: Videocardz
Pokdepinion: Interesting application of the L4 cache. We might be seeing ASIC-like functionalities on caches at some point perhaps?
