AMD recently was granted a patent in the European Patent Office, titled “Multi-Chip Package With Offset 3D Structure” – and this patent gives us a glimpse on what the chipmaker will do next in the chip packaging technology.
What’s Next For AMD’s Chiplets?
The patent diagram (discovered by @coreteks) looks like this: several chiplets are laid out in different spots on the CPU substrate, with one big chiplet (shown as dashed lines) stacked below them partially (Note: based on the subsequent diagrams, we believe coreteks incorrectly described the stacking order), and they all will then be connected through a maze of interconnects under them. Like today’s chip stacking technologies, this aims to further improve on chip efficiency, and more importantly, cut down on latency.
One of the unique quirks of Ryzen CPUs is the slightly higher latency than monolithic chips due to extra time required to physically travel through the other chip for communications, and while AMD has done a good job of mostly masking that deficit, it’s ultimately one of the shortcomings that is ideally to be eliminated if the technology allows it.
Aside from performance implications, another big factor to chiplet designs like this is cost. One reason why AMD was able to massively undercut Intel in pricing back when Ryzen was first launched in the market was due to the simplicity of manufacturing smaller dies, which minimizes defects and ultimately cost. A design like this one can potentially make the dies even smaller (by further splitting each functions of the chip) and offer greater flexibility for the chipmaker to add and remove parts of the CPU as they see fit.
However, it’s worth noting that this patent was applied five years ago and has only been recently approved – it’s unclear if AMD has ever made any functioning prototypes on this design nor are there any announced plans to do so. Patents like these are not always a guarantee to turn into a product, but it’s reasonable to say that this technology in particular might not be as far-fetched as one would believe.
Source: igor’sLAB
Pokdepinion: I do think this will be far beyond just the 3D V-Cache, this might be how future CPUs look like ultimately.
