Cadence has announced that its PCIe 6.0 PHY and controller IP, implemented in the TSMC N3 process, achieved first-pass compliance success at the PCI-SIG compliance workshop held in late July 2026. The event marked the industry’s first official compliance testing workshop for the PCIe 6.0 specification, and the Cadence PCIe 6.0 x8 subsystem was tested at the full specification speed of 64 GT/s.
Cadence PCIe 6.0 Subsystem
The complete solution, comprising both PHY and controller, passed all official PCIe 6.0 compliance tests and has been added to PCI-SIG’s Integrators List. The result positions Cadence’s subsystem as a production-ready option for SoC providers targeting AI and high-performance computing applications.
The Cadence PCIe 6.0 subsystem is built entirely in silicon on TSMC’s N3 process node and is certified for x8 configuration. It incorporates ADC and DSP-based equalization alongside firmware-optimized SerDes operation, and supports multi-protocol flexibility. The solution is also optimized for low power consumption, with support for the latest PCI-SIG engineering change notices.
Cadence says it prepared for the compliance workshop by working closely with PCI-SIG, test equipment providers, and industry partners in the months prior to the formal evaluation to identify and resolve potential issues before the official compliance assessment. PCIe 6.0, being doubly faster than PCIe 5.0 standards, is designed to address the growing demand for high-bandwidth connectivity in AI datacenters and high-performance computing systems.
Positron AI has already licensed Cadence’s SerDes IP for the PCIe 6.0 specification for use in its AI inference accelerator chip, citing the production-grade silicon implementation and interoperability testing as key factors in its decision. The complete Cadence PCIe 6.0 subsystem, including PHY and controller, is available now for SoC providers to design in.
Pokdepinion: We somehow keep squeezing more speed into more or less the same piece of copper.
