Thunderbolt 5 specs accidentally leaked by Intel VP
Intel VP Gregory M Bryant has reportedly leaked out some specifications of Thunderbolt 5 in a tweet, before quickly removing it. But as usual, what goes online never truly disappears. David Schor from WikiChip spotted the image before it was removed, and shared it with Dr. Ian Cutress of AnandTech.
As you might know, Thunderbolt 4 doesn’t bring any extra raw bandwidth over Thunderbolt 3, but that might change with Thunderbolt 5. According to the slide that was spotted, Intel is working to bring 80Gbps speeds, while still supporting the existing USB-C ecosystem, which is great news. Whether it will make getting USB-C cables even more confusing remains to be seen, but let’s cross the bridge when we get there.
Another tidbit from the slide is that Thunderbolt 5 will harness novel PAM-3 modulation technology. PAM-3 modulation will transmit three bits per cycle, versus the two bits per cycle that Non-Return-to-Zero (NRZ) modulation offers in the existing solutions.
It’s interesting that they went with PAM-3 instead of PAM-4, which would offer an even greater increase in bandwidth, but AnandTech explains that PAM-3 enjoys the same tolerances that NRZ has when it comes to signaling. Meanwhile if Intel went with PAM-4 modulation, they will have to deal with more limitations, among which is increased power consumption due to the need of higher voltages.
It also seems like Intel is making their test Thunderbolt 5 controller at TSMC on the N6 node. Intel has previously revealed that they will be making certain non-core products at TSMC, so the upcoming Thunderbolt controller chip might be one of them.
It’s unclear when will Intel reveal more about Thunderbolt 5. Intel is going to unveil their 12th Gen Intel Alder Lake processors later this year, so we might see Intel talk more about this then. Or maybe Thunderbolt 5 will arrive later during CES 2022. Well, all we have to do is wait.
Pokdepinion: I wonder if Thunderbolt 5 will allow for external GPUs to deliver better performance since we are now at about PCIe 3.0 x8 levels of speeds.